The present invention relates to an improvement in a logic circuit such as an input gate of a CMOS LSI and, more particularly, to a logic circuit for stabilizing and, input logic threshold level, in the face of fluctuations in a power source voltage.
CMOS inverter 10 is a typical conventional CMOS LSI input gate, which consists of p- and n-channel CMOS transistors P1 and N1, as is shown in FIGS. 1 or 2. A gate input to inverter 10 is either a TTL level input signal (e.g., RST) of active low or one (e.g., RST) of active high supplied from external signal input pad 11. If system clock .phi. (FIG. 3A) is supplied to a clock input terminal of an LSI having the input gate shown in FIG. 1, the low active period of the RST signal (FIG. 3B) is set to coincide with, for example, two cycles of clock .phi.. Similarly, if system clock .phi. (FIG. 4A) is supplied to a clock input terminal (not shown) of an LSI having the input gate shown in FIG. 2, the high active period of the RST signal (FIG. 4B) is set to coincide with, for example, two cycles of clock .phi..
When, in the LST having the input gate of low active operation (as shown in FIG. 1), buffers having a large drive capacity (i.e., the ratio W/L of gate width W to gate length L is large) are driven simultaneously, circuit-ground potential VSS often varies from 0 V to 1 V (this phenomenon is called potential floating). In this case, the current drive capacity of transistor N1 is degraded, and switching threshold voltage VM of inverter 10 is shifted from a predetermined level to high level. When power source potential VDD is lowered from, for example, 5 V to 4 V, upon simultaneous operation of the buffers, voltage VM is shifted from the predetermined level to lower level.
Assume that threshold voltage VM is lowered during the low active period of the RST signal, upon lowering of the VDD potential. In this case, CMOS inverter 10 detects the RST signal as a high level signal, although the RST signal is actually set at low level. If the low active period of the RST signal is long enough (i.e., 2-cycle period of clock .phi.) so that temporary noise superposed on the input to inverter 10 attenuates, an accurate logic level can eventually be detected. When voltage VM is elevated due to floating of the VSS potential during the low active period of the RST signal, inverter 10 can accurately detect the low level of the RST signal. However, if voltage VM is elevated due to floating of the VSS potential during the nonactive period of the RST signal, inverter 10 tends to erroneously detect the RST signal as a low level signal, although it is actually set at high level.
Similarly, if, in the LSI having the input gate of active high operation (as shown in FIG. 2), threshold voltage VM is lowered due to lowering of the VDD potential during the nonactive period of the RST signal, inverter 10 tends to erroneously detect the RST signal as a high level signal, although it is actually set at low level.
Fluctuations, such as floating of the VSS potential and lowering of the VDD potential, increase with any increase in the number of I/O pins of the LSI, that is, any increase in the number of I/O buffers.